| 1. |
- Grimm, Christoph, et al.
(författare)
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C-Based Design of Embedded Systems - Editorial
- 2008
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Ingår i: EURASIP Journal on Embedded Systems. - : Springer Science and Business Media LLC. - 1687-3955 .- 1687-3963. ; :1, s. 243890-
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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| 2. |
- Mathaikutty, Deepak A., et al.
(författare)
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SML-Sys : a functional framework with multiple models of computation for modeling heterogeneous system
- 2008
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Ingår i: Design automation for embedded systems. - : Springer Science and Business Media LLC. - 0929-5585 .- 1572-8080. ; 12:1-2, s. 1-30
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Tidskriftsartikel (refereegranskat)abstract
- System-on-Chip and other complex distributed hardware/software systems contain heterogeneous components. High-level modeling of such systems require frameworks that provide designers with the ability to express concepts of models of computation (MoC)s as modeling constructs. Many system-level modeling frameworks and corresponding modeling notations such as Ptolemy II and SystemC-H facilitate multi-MoC modeling but are based on imperative programming languages (C++, Java, etc). In such frameworks, the computation and communication aspects between the components of models get intertwined thereby hindering its amenability to formal analysis. In this work, we illustrate function-based semantic definitions of MoCs, which are formulated in a functional framework called SML-Sys. We illustrate through a number of examples how to create system models using this functional programming paradigm.
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| 3. |
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| 4. |
- Mathaikutty, Deepak Abraham, et al.
(författare)
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UMoC++ : A C++-Based Multi-MoC Modeling Environment
- 2006
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Ingår i: Advances in Design and Specification Languages for SoCs. - : Springer Publishing Company. ; , s. 115-130
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Konferensbidrag (refereegranskat)abstract
- System-on-chip (SoC) and other complex distributed hardware/software systemscontain heterogeneous components that necessitate frameworks capable of expressingheterogeneous models of computation (MoCs) for modeling their functionalities.System-level design languages (SLDLs) that facilitate multi-MoCmodeling should have well-defined semantics and should be readily subjectedto formal analysis to handle the design complexity. As a result, we follow themulti-MoC paradigm based on timing abstraction and functional parameterizationsthat have rigorous denotational semantics, which are compliant to functionalidioms as shown in functional frameworks such as ForSyDe and SML-Sys.However, functional frameworks are not widely used in the industry due toissues related to efficiency and interoperability with other widely used SLDLs.This imposes a requirement for an imperative language-based implementationof these generic MoCs that offers all the advantages of the underlying formalsemantics. In this chapter, we formulate the basis for having generic MoCs in animperative language and describe the implementation of an untimed modelingframework called UMoC++.
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| 5. |
- Mathaikutty, Deepak A., et al.
(författare)
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UMoC plus plus : A C plus plus -based Multi-MoC modeling environment
- 2006
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Ingår i: APPLICATIONS OF SPECIFICATION AND DESIGN LANGUAGES FOR SOCS. - Dordrecht : SPRINGER. ; , s. 115-130
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Konferensbidrag (refereegranskat)abstract
- System-on-chip (SoC) and other complex distributed hardware/software systems contain heterogeneous components that necessitate frameworks capable of expressing heterogeneous models of computation (MoCs) for modeling their functionalities. System-level design languages (SLDLs) that facilitate multi-MoC modeling should have well-defined semantics and should be readily subjected to formal analysis to handle the design complexity. As a result, we follow the multi-MoC paradigm based on timing abstraction and functional parameterizations that have rigorous denotational semantics, which are compliant to functional idioms as shown in functional frameworks such as ForSyDe and SML-Sys. However, functional frameworks are not widely used in the industry due to issues related to efficiency and interoperability with other widely used SLDLs. This imposes a requirement for an imperative language-based implementation of these generic MoCs that offers all the advantages of the underlying formal semantics. In this chapter, we formulate the basis for having generic MoCs in an imperative language and describe the implementation of an untimed modeling framework called UMoC++.
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| 6. |
- Mathaikutty, Deepak, et al.
(författare)
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EWD : A metamodeling driven customizable multi-MoC system modeling framework
- 2007
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Ingår i: ACM Transactions on Design Automation of Electronic Systems. - : Association for Computing Machinery (ACM). - 1084-4309 .- 1557-7309. ; 12:3, s. 1255470-
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Tidskriftsartikel (refereegranskat)abstract
- We present the EWD design environment and methodology, a modeling and simulation framework suited for complex and heterogeneous embedded systems with varying degrees of expressibility and modeling fidelity. This environment promotes the use of multiple models of computation (MoCs) to support heterogeneity and metamodeling for conformance tests of syntactic and static semantics during the process of modeling. Therefore, EWD is a multiple MoC rnodeling and simulation framework that ensures conformance of the MoC formalisms during model construction using a metamodeling approach. In addition, EWD provides a suite of translation tools that generate executable models for two simulation frameworks to demonstrate its language-independent modeling framework. The EWD methodology uses the Generic Modeling Environment for customization of the MoC-specific modeling syntax into a visual representation. To embed the execution semantics of the MoCs into the models, we have built parsing and translation tools that leverage an XML-based interoperability language. This interoperability language is then translated into executable Standard ML or Haskell models that can also be analyzed by existing simulation frameworks such as SML-Sys or ForSyDe. In summary, EWD is a metamodeling driven multitarget design environment with multi-MoC modeling capability.
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| 7. |
- Raudvere, Tarvo, 1976-
(författare)
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System Level Techniques for Verification and Synchronization after Local Design Refinements
- 2007
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Today's advanced digital devices are enormously complex and incorporate many functions. In order to capture the system functionality and to be able to analyze the needs for a final implementation more efficiently, the entry point of the system development process is pushed to a higher level of abstraction. System level design methodologies describe the initial system model without considering lower level implementation details and the objective of the design development process is to introduce lower level details through design refinement. In practice this kind of refinement process may entail non-semantic-preserving changes in the system description, and introduce new behaviors in the system functionality. In spite of new behaviors, a model formed by the refinement may still satisfy the design constraints and to realize the expected system. Due to the size of the involved models and the huge abstraction gap, the direct verification of a detailed implementation model against the abstract system model is quite impossible. However, the verification task can be considerably simplified, if each refinement step and its local implications are verified separately. One main idea of the Formal System Design (ForSyDe) methodology is to break the design process into smaller refinement steps that can be individually understood, analyzed and verified. The topic of this thesis is the verification of refinement steps in ForSyDe and similar methodologies. It proposes verification attributes attached to each non-semantic-preserving transformation. The attributes include critical properties that have to be preserved by transformations. Verification properties are defined as temporal logic expressions and the actual verification is done with the SMV model checker. The mapping rules of ForSyDe models to the SMV language are provided. In addition to properties, the verification attributes include abstraction techniques to reduce the size of the models and to make verification tractable. For computation refinements, the author defines the polynomial abstraction technique, that addresses verification of DSP applications at a high abstraction level. Due to the size of models, predefined properties target only the local correctness of refined design blocks and the global influence has to be examined separately. In order to compensate the influence of temporal refinements, the thesis provides two novel synchronization techniques. The proposed verification and synchronization techniques have been applied to relevant applications in the computation area and to communication protocols.
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